Embodiments of the present invention relate to a method for forming a semiconductor device, and more particularly to a method for forming a semiconductor device so as to simplify a fabrication process by changing a mask process.
Recently, most of electronic appliances comprise a semiconductor device. The semiconductor device comprises electronic elements such as a transistor, a resistor and a capacitor. These electronic appliances are designed to perform a partial function of electronic elements, and integrated on a semiconductor substrate. For example, an electronic appliance such as a computer or a digital camera includes a memory chip for storing information and a processing chip for controlling information. The memory chip and the processing chip include electronic elements integrated on a semiconductor substrate.
The semiconductor devices have a need for an increase in an integration degree, in order to satisfy consumer demands for superior performances and low prices. Such an increase in the integration degree of a semiconductor device entails a reduction in a design rule, causing a pattern size of a semiconductor device to decrease. An entire chip area increases as a memory capacity of a semiconductor device increases. However, a greater number of patterns should be formed in a limited cell area in order to achieve a desired memory capacity, and there is a need for formation of a finer pattern having a reduced critical dimension.
However, an exposure device for implementing a fine pattern required for the increasing integration degree of a semiconductor device does not catch up with rapid development of associated technology. Specifically, when forming a photoresist pattern including silicon using a known exposure device which performs an exposure and development process on the photoresist film including silicon, there is a limitation in resolution capability of the exposure device.
An exemplary method for forming such a fine pattern is a Double Patterning Technology (DPT). The DPT may be classified into a Double Expose Etch Technology (DE2T) and a Spacer Patterning Technology (SPT) that uses a spacer. The DE2T exposes and etches a first pattern having a double cycle of a pattern, and exposes and etches a second pattern having the double cycle of the pattern between the first patterns.
Meanwhile, in order to form more memory cells in one wafer, the chip size decrease or the cell structure is changed. For example, a method for changing a plane arrangement of active regions, a method for changing a cell layout, and the like may be used. In order to implement the above-mentioned methods, a known method, that changes a layout format of the active region from a 8F2 layout to a 6F2 layout, may be used. Generally, the 6F2-layout semiconductor device has a length of 3F in a longitudinal direction of a bit line, and has a length of 2F in a longitudinal direction of a word line. In order to implement the 6F2-layout semiconductor device, the active regions are not parallel to each other in a horizontal direction and has an oblique structure in which a long axis of the active regions is obliquely arranged.
However, the developing speed of a fabrication technology for forming a pattern, including the lithography technology, is slower than the increasing speed of the integration degree of the semiconductor device. Therefore, in case of forming of the oblique-shaped active region, a spacer patterning technology (SPT) method is being used, and in order to separate interconnected patterns from each other, a method for removing some parts of the active region that has been extended in the diagonal direction using the cutting mask may be used.